1. Field of the Invention
The invention relates to a delay circuit for delaying a digital signal by a selectable fraction of the sampling period of the digital signal.
2. Description of the Related Art
Such a delay circuit is disclosed in European Patent EP-B-0,181,953, corresponding to U.S. Pat. No. 4,760,542. In FIG. 3 of that patent, a sample halfway between two original samples is obtained by means of an averager. The averager comprises a peaking circuit to improve the frequency characteristic of the averager. Subsequently, a sample at a selectable position between one of the original samples and the obtained sample halfway between the two original samples is obtained by multiplying the difference between the sample halfway and the one original sample by a factor which depends on the desired delay, and by adding the result to the one original sample.
The frequency characteristic of this delay circuit appears to depend too much on the magnitude of the selected delay, which causes distortions in the output signal of the delay circuit. Moreover, EP-B-0,181,953 provides no indications of the way in which the peaking factor should be chosen.
U.S. Pat. No. 4,694,414 discloses a delay interpolation filter which provides for amplitude and phase compensation, in which a two-point linear interpolation filter imparts delay to an input signal. The delay is proportional to the value of a delay control signal. In an attempt to minimize errors in both amplitude and phase, a correction term is added to the delayed signal. The correction signal is provided by applying the input signal to a further filter and multiplier connected in cascade. The further filter is a linear phase filter having a zero response at zero frequency and a delay equal to an odd multiple of the sampling period Ts of the input signal. The multiplier is controlled so as to vary the amplitude of the compensating signal as a non-linear function of the delay control signal in order to provide maximum amplitude compensation at delays corresponding to odd multiples of Ts/2 and zero amplitude compensation at delays equal to integral multiples of Ts.
FIG. 9 of the above-mentioned US Patent shows that the amplitude error at 5 MHz is -3 dB when the signal is sampled at a 14.4 MHz clock frequency, which is too large when the interpolation filter is to be used in video applications with a dynamically changing delay, as is required when a signal, which has originally been sampled at a 13.5 MHz sampling frequency, is interpolated to another sampling frequency. When it is attempted to decrease the amplitude error, the corresponding correction of the phase is complicated. Moreover, the non-linear function used to vary the amplitude of the compensating signal, yields results which are difficult to predict.